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Integrated Circuit Systems, Inc.
ICS94258
Programmable System Clock Chip for PIII Processor
Recommended Application: ALI 1644 style chipset Output Features: * 2 - CPU clocks (including 1 free running) @ 2.5V * 13 - SDRAM @ 3.3V * 7 - PCI (including 1 free running and 1 early selectable free running) @ 3.3V * 2 - AGP @ 3.3V * 1 - IOAPIC 14.318MHz @ 2.5V * 1 - 48MHz, @ 3.3V * 1 - REF 14.318MHZ @ 3.3V, (selectable strength 1X or 2X) through I2C programming Features: * Programmable ouput frequency * Programmable ouput rise/fall time * Programmable CPU, SDRAM, PCI and AGP skew * Real time system reset output * Spread spectrum for EMI control typically by 7dB to 8dB, with programmable spread percentage * Watchdog timer technology to reset system if over-clocking causes malfunction * Uses external 14.318MHz crystal Skew Specifications: * CPU - CPU: <250ps * PCI - PCI: <500ps * SDRAM - SDRAM: <250ps * AGP - AGP: <500ps * PCI - AGP: <750ps * CPU - SDRAM:<350ps * CPU - PCI: <3ns
Pin Configuration
48-Pin 300mil SSOP & TSSOP
Notes: REF0 can be 1X or 2X strength controlled by I2C. * Internal Pull-up Resistor of 120K to VDD ** Internal Pull-down of 120K to GND 1. This input has 2X drive strength
Block Diagram
Functionality
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU SDRAM 66.66 66.66 66.66 100.00 100.00 66.66 100.00 100.00 100.00 133.33 133.33 66.66 133.33 100.00 133.33 133.33 66.66 66.66 66.66 100.00 100.00 66.66 100.00 100.00 100.00 133.33 133.33 66.66 133.33 100.00 133.33 133.33
Note: PCICLK = 33.33MHz , AGP = 66.66MHz
94258 Rev B - 12/19/01 Third party brands and names are the property of their respective owners.
ICS94258
Pin Descriptions
PIN NUMBER 1, 45 2 4 5 3, 11, 16, 23, 29, 34, 41, 48 6, 8, 17, 21, 28, 35, 40 7 9 10 12 PIN N AME V DDL IOAPIC X1 X2 GN D VD D FS0 REF
2, 3
TYPE PWR OUT IN OUT PWR PWR IN OUT IN OUT OUT OUT IN OUT OUT OUT OUT IN OUT OUT
DESCRIPTION Pow er supply pins, nominal 2.5V 2.5V clock outputs Crystal input,nominally 14.318M Hz. Crystal output, nominally 14.318M H z. G round pins Pow er supply pins, nominal 3.3V Frequency select pin, 1X or 2X strength (default = 2X). 14.318 M H z reference clock. Frequency select pin. A GP outputs defined as 2X PCI frequency. These may not be stopped. A GP outputs defined as 2X PCI frequency. These may not be stopped. Free running PCICLK not stoped by PCI_STOP# Frequency select pin. PCI clock output Real time system reset signal for frequency value or watchdog timmer timeout. This signal is active low. Output is selectable via I C Byte 5 bit7 PCI clock outputs. PCI clock output. Function select pin, 1=Desktop M ode, 0=M obile M ode. Free running early PCI clock output (default) PCI clock output. A synchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down w ill not be greater than 3ms. (See M ODE table for further information.) PCI clock output. This pin is active when M ODE = 0 (default) Frequency select pin. 48M Hz output clock. Clock input of I C input, 5V tolerant input A synchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down w ill not be greater than 3ms. (See M ODE table for further information.) SDRAM clock output. This pin is active when M ODE = 1. This asynchronous input halts CPU clock at logic "0" level when driven low, the stop selection can be programmed through I C. This is activated when M ODE = 0 (default) SDRAM clock output. This pin is active when M ODE = 1. Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, w hen input low. This is activated when M OD E = 0 (default) SDRAM clock output. This pin is active when M ODE = 1. Selects EPCICLK _F This pin is active when M O DE = 0 (default). SDRAM clock output. This pin is active when M ODE = 1. SDRAM clock outputs. D ata pin for I C circuitry 5V tolerant Free running CPU clock. N ot affected by CPU_STO P#. 2.5V CPU clock.
2 2 2 2
FS1 AG P0 AG P1 PCICLK_F FS2 PCICLK2
1, 3
2, 3
15
RESET# PCICLK (1, 0) PCICLK3 M OD E EPCICLK_F PCICLK4
1 1, 3
14, 13 18 19
20
PD #
IN
PCICLK5 22 24 FS3 48M Hz SCLK
2, 3
OUT IN OUT IN
25
PD #
1
IN
SD RA M 12 CPU_STOP# SD RA M 11 27 PCI_STOP# SD RA M 10 SELPCI_F SDRAM 9 SDRAM ( 8:0 ) SDA TA CPUCLK _F CPUCLK
1 1
OUT IN OUT IN OUT IN OUT OUT I/O OUT OUT
26
30 31, 32, 33, 36, 37, 38, 39, 42, 43 44 46 47
Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low. 3: Internal Pull-down resistor of 120K to GND on indicated inputs.
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ICS94258
General Description
The ICS94258 is a main clock synthesizer chip for PIII based systems with ALI 1644 style chipset. This provides all clocks required for such a system. The ICS94258 belongs to ICS new generation of programmable system clock generators. It employs serial programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over clocking.
Mode Pin - Power Management Input Control
MODE, Pin 18 (Latched Input) 0 1 Pin 20 PCICLK5 (Output) PD# (Input) Pin 25 PD# (Input) SDRAM12 (Output) Pin 26 CPU_STOP# (Input) SDRAM11 (Output) Pin 27 PCI_STOP# (Input) SDRAM10 (Output) Pin 30 SELPCI_F (Input) SDRAM9 (Output)
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ICS94258
General I2C serial interface information for the ICS94258 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending Byte 0 through Byte 20 (see Note) ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends Byte 0 through byte 8 (default) ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK
ACK ACK ACK ACK ACK ACK ACK
How to Read:
Controlle r (Host) Start Bit Address D3 (H ) ICS (Sla ve /Re ce ive r)
ICS (Slave/Receiver)
ACK
A CK Byte Count Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 ACK If 7H has been written to B8 ACK Byte 7
Byte 18 ACK Byte 19 ACK Byte 20 ACK Stop Bit
If 12H has been written to B8 ACK If 13H has been written to B8 ACK If 14H has been written to B8 ACK Stop Bit Byte18 Byte 19 Byte 20
*See notes on the following page.
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ICS94258
Brief I2C registers description for ICS94258 Programmable System Frequency Generator
Register Name Functionality & Frequency Select Register Output Control Registers Byte 0 Description Output frequency, hardware / I C frequency select, spread spectrum & output enable control register. Active / inactive output control registers/latch inputs read back. Byte 11 bit[7:4] is ICS vendor id - 1001. Other bits in this register designate device revision ID of this part. Writing to this register will configure byte count and how many byte will be read back. Do not write 00 H to this byte. Writing to this register will configure the number of seconds for the watchdog timer to reset. Watchdog enable, watchdog status and programmable 'safe' frequency' can be configured in this register. This bit select whether the output frequency is control by hardware/byte 0 configurations or byte 11&12 programming. These registers control the dividers ratio into the phase detector and thus control the VCO output frequency. These registers control the spread percentage amount. Increment or decrement the group skew amount as compared to the initial skew. These registers will control the output rise and fall time.
2
PWD Default See individual byte description See individual byte description See individual byte description
1-6
Vendor ID & Revision ID Registers
7
Byte Count Read Back Register
8
08 H
Watchdog Timer Count Register
9
10 H
Watchdog Control Registers 10 Bit [6:0]
000,0000
VCO Control Selection Bit
10 Bit [7]
0
VCO Frequency Control Registers Spread Spectrum Control Registers Group Skews Control Registers Output Rise/Fall Time Select Registers
11-12
Depended on hardware/byte 0 configuration Depended on hardware/byte 0 configuration See individual byte description See individual byte description
13-14
15-16 17-20
Notes:
1. 2. 3. 4. 5. 6.
7.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Readback will support standard SMBUS controller protocol. The number of bytes to readback is defined by writing to byte 8. When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte 14 is written but not 15, neither byte 14 or 15 will load into the receiver. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
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ICS94258
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit D e s cription FS3 FS2 FS1 FS0 CPUCLK SDRAM PCICLK (MHz) (MHz) (MHz) Bit2 Bit7 Bit6 Bit5 Bit4 0 0 0 0 0 66.66 66.66 33.33 0 0 0 0 1 66.66 100.00 33.33 0 0 0 1 0 100.00 66.66 33.33 0 0 0 1 1 100.00 100.00 33.33 0 0 1 0 0 100.00 133.33 33.33 0 0 1 0 1 133.33 66.66 33.33 0 0 1 1 0 133.33 100.00 33.33 0 0 1 1 1 133.33 133.33 33.33 0 1 0 0 0 66.66 66.66 33.33 0 1 0 0 1 66.66 100.00 33.33 0 1 0 1 0 100.00 66.66 33.33 0 1 0 1 1 100.00 100.00 33.33 0 1 1 0 0 100.00 133.33 33.33 0 1 1 0 1 133.33 66.66 33.33 0 1 1 1 0 133.33 100.00 33.33 0 1 1 1 1 133.33 133.33 33.33 1 0 0 0 0 69.99 69.99 35.00 1 0 0 0 1 69.99 105.00 35.00 1 0 0 1 0 105.00 69.99 35.00 1 0 0 1 1 105.00 105.00 35.00 1 0 1 0 0 105.00 140.00 35.00 1 0 1 0 1 140.00 69.99 35.00 1 0 1 1 0 140.00 105.00 35.00 1 0 1 1 1 140.00 140.00 35.00 1 1 0 0 0 73.33 73.33 36.66 1 1 0 0 1 73.33 110.00 36.66 1 1 0 1 0 110.00 73.33 36.66 1 1 0 1 1 110.00 110.00 36.66 1 1 1 0 0 110.00 146.66 36.66 1 1 1 0 1 146.66 73.33 36.66 1 1 1 1 0 146.66 110.00 36.66 1 1 1 1 1 146.66 146.66 36.66 0 - Frequency is selected by hardware select, Latched Inputs 1 - Frequency is selected by Bit 2, 7:4 0 - Normal 1 - Spread Spectrum Enabled 0 - Running 1- Tristate all outputs AGP (MHz) 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 69.99 69.99 69.99 69.99 69.99 69.99 69.99 69.99 73.33 73.33 73.33 73.33 73.33 73.33 73.33 73.33 Spread Precentage +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread 0 to - 0.5% Down Spread 0 to - 0.5% Down Spread 0 to - 0.5% Down Spread 0 to - 0.5% Down Spread 0 to - 0.5% Down Spread 0 to - 0.5% Down Spread 0 to - 0.5% Down Spread 0 to - 0.5% Down Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread PWD
Bit 2, Bit 7:4
00000 Note1
Bit 3 Bit 1 Bit 0
0 0 0
Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3. The I2C readback of the power up default indicates the revision ID in bits 2, 7:4 as shown.
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ICS94258
Byte 1: CPU, Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 10 9 22 2 7 46 47 PWD X 1 1 1 1 0 1 1 FS3# AGP1 AGP0 48MHz IOAPIC REF - 1X or 2X d e fa u l t = 0 = 2 X CPUCLK_F CPUCLK DESCRIPTION
Byte 2: PCI, Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 18 20 19 18 15 14 13 12 PWD 0 1 1 1 1 1 1 1 DESCRIPTION MODE# PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 PCICLK_F
Byte 3: SDRAM, Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 31 30 27 26 25 PWD X X X 1 1 1 1 1 FS0# FS1# FS2# SDRAM8 SDRAM9 SDRAM10 SDRAM11 SDRAM12 DESCRIPTION
Byte 4: Reserved , Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 43 42 39 38 37 36 33 32 PWD 1 1 1 1 1 1 1 1 DESCRIPTION SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7
Byte 5: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
PIN# PWD
15 30 1 1 1 1 1 1 0
DESCRIPTION
1 = PCICLK2, 0 = RESET# (Reserved) SDRAM9/SELPCI_F (default = 1 = SELPCI_F) (Reserved) (Reserved) (Reserved) Bit (1:0) = 00 CPU_STOP will stop CPU clocks Bit (1:0) = 01 CPU_STOP will stop CPU, SDRAM, AGP clocks Bit (1:0) = 10 CPU_STOP will stop CPU, SDRAM clocks Bit (1:0) = 11 CPU_STOP will stop CPU, AGP clocks
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Notes:
PIN# -
PWD 0 0 0 0 0 1 1 1
DESCRIPTION R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e )
Bit 0
-
0
1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
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ICS94258
Byte 7: Vendor ID and Revision ID Register
Byte 8: Byte Count and Read Back Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 1 X X X X X
Description Vendor ID Vendor ID Vendor ID Revision ID Revision ID Revision ID Revision ID Revision ID
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 0 1 0 0 0
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Byte 9: Watchdog Timer Count Register
Byte 10: VCO Control Selection Bit & Watchdog Timer Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 1 0 0 0 0
Description The decimal representation of these 8 bits correspond to how many 290ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 16X 290ms = 4.64 seconds.
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 1 0 0 0 0
Description 0=Hw/B0 freq / 1=B11 & 12 freq WD Enable 0=disable / 1=enable WD Status 0=normal / 1=alarm WD Safe Frequency, Byte 0 bit 2 WD Safe Frequency, FS3 WD Safe Frequency, FS2 WD Safe Frequency, FS1 WD Safe Frequency, FS0
Note: FS values in bit (0:4) will correspond to Byte 0 FS values. Default safe frequency is same as 00000 entry in byte0.
Byte 11: VCO Frequency Control Register
Byte 12: VCO Frequency Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description VCO Divider Bit0 REF Divider Bit6 REF Divider Bit5 REF Divider Bit4 REF Divider Bit3 REF Divider Bit2 REF Divider Bit1 REF Divider Bit0
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description VCO Divider Bit8 VCO Divider Bit7 VCO Divider Bit6 VCO Divider Bit5 VCO Divider Bit4 VCO Divider Bit3 VCO Divider Bit2 VCO Divider Bit1
Note: The decimal representation of these 7 bits (Byte 11 (6:0)) + 2 is equal to the REF divider value .
Notes: 1. PWD = Power on Default
Note: The decimal representation of these 9 bits (Byte 12 bit (7:0) & Byte 11 bit (7) ) + 8 is equal to the VCO divider value. For example if VCO divider value of 36 is desired, user need to program 36 - 8 = 28, namely, 0, 00011100 into byte 12 bit & byte 11 bit 7.
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ICS94258
Byte 13: Spread Sectrum Control Register Byte 14: Spread Sectrum Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Spread Spectrum Bit7 Spread Spectrum Bit6 Spread Spectrum Bit5 Spread Spectrum Bit4 Spread Spectrum Bit3 Spread Spectrum Bit2 Spread Spectrum Bit1 Spread Spectrum Bit0
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Reserved Reserved Reserved Spread Spectrum Bit12 Spread Spectrum Bit11 Spread Spectrum Bit10 Spread Spectrum Bi 9 Spread Spectrum Bit8
Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread percentage may cause system failure.
Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread percentage may cause system failure.
Byte 15: Output Skew Control
Byte 16: Output Skew Control
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 1 1 1 1 1 1 1 1
Description CPUCLK Skew Control CPUCLK_F Skew Control SDRAM0 Skew Control SDRAM (12:1) Skew Control
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD Description 0 1 PCICLK (5:0, F) Skew Control 0 0 0 1 AGP (1:0) Skew Control 0 0
Byte 17: Output Rise/Fall Time Select Register
Byte 18: Output Rise/Fall Time Select Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 1 0 1 0 1 0 1 0
Description CPUCLK Slew Rate Control CPUCLK_F Slew Rate Control PCICLK_F Slew Rate Control PCICLK (5:0) Slew Rate Control
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 1 0 1 0 1 0 1 0
Description SDRAM0 Skew Control SDRAM (12:1) Skew Control AGP (1:0) Slew Rate Control 48MHz Slew Rate Control
Notes: 1. PWD = Power on Default 2. The power on default for byte 13-20 depends on the harware (latch inputs FS(4:0)) or I2C (Byte 0 bit (1:7)) setting. Be sure to read back and re-write the values of these 8 registers when VCO frequency change is desired for the first pass. 3. If Byte 8 bit 7 is driven to "1" meaning programming is intended, Byte 21-24 will lose their default power up value.
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ICS94258
Byte 19: Reserved Register Byte 20: Reserved Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Note: Byte 19 and 20 are reserved registers, these are VCO Programming Constrains VCO Frequency ...................... 150MHz to 500MHz VCO Divider Range ................ 8 to 519 REF Divider Range ................. 2 to 129 Phase Detector Stability .......... 0.3536 to 1.4142 Useful Formula VCO Frequency = 14.31818 x VCO/REF divider value Phase Detector Stabiliy = 14.038 x (VCO divider value)-0.5 To program the VCO frequency for over-clocking. 0. Before trying to program our clock manually, consider using ICS provided software utilities for easy programming.
unused registers writing to these registers will not affect device performance or functinality.
1. Select the frequency you want to over-clock from with the desire gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by writing to byte 0, or using initial hardware power up frequency. 2. Write 0001, 1001 (19H) to byte 8 for readback of 21 bytes (byte 0-20). 3. Read back byte 11-20 and copy values in these registers. 4. Re-initialize the write sequence. 5. Write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired VCO & REF divider values. 6. Write to byte 13 to 20 with the values you copy from step 3. This maintains the output spread, skew and slew rate. 7. The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needed to be changed again, user only needs to write to byte 11 and 12 unless the system is to reboot. Note: 1. User needs to ensure step 3 & 7 is carried out. Systems with wrong spread percentage and/or group to group skew relation programmed into bytes 13-16 could be unstable. Step 3 & 7 assure the correct spread and skew relationship. 2. If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctly. 3. Follow min and max VCO frequency range provided. Internal PLL could be unstable if VCO frequency is too fast or too slow. Use 14.31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz). 4. ICS recommends users, to utilize the software utility provided by ICS Application Engineering to program the VCO frequency. 5. Spread percent needs to be calculated based on VCO frequency, spread modulation frequency and spreadamount desired. See Application note for software support.
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ICS94258
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V DD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . 0C to +70C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current SYMBOL VIH VIL IIH VIN = VDD IIL1 IIL2 CONDITIONS MIN 2 VSS-0.3 -5 -5 -200 101 120 140 11 200 14.32 5 6 45 3 350 1.2 3 750 125 150 175 70 600 mA MHz pF pF pF ms ps ns ps mA TYP MAX UNITS VDD+0.3 V 0.8 V 5 mA mA
VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0; CPU=66 MHz, SDRAM=66 MHz
Operating Supply Current
IDD3.3OP
IDD2.5OP Powerdown Current Input Frequency Input Capacitance
1 1
CL = 0; CPU=100 MHz, SDRAM=66, 100, 133 MHz CPU=133 MHz, SDRAM=133 MHz CL =0; CPU=66-133 MHz, SDRAM=100 CL = 0 pF; Input address to VDD or GND VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins From VDD = 3.3 V to 1% target frequency VT = 1.25 V/ VT = 1.5 V VT = 1.25 V/ VT = 1.5 V VT = 1.5 V
IDD3.3PD Fi CIN COUT CINX TSTAB tskCPU-SDR tskCPU-PCI tskAGP-PCI
27
Clk Stabilization
CPU to SDRAM CPU to PCI AGP to PCI
1
Guaranteed by design, not 100% tested in production.
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ICS94258
Electrical Characteristics - CPU
TA = 0 - 70 C; VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS IOH = -12.0 mA Output High Voltage VOH2B Output Low Voltage VOL2B IOL = 12 mA IOH2B VOH = 1.7 V Output High Current IOL2B VOL = 0.7 V Output Low Current Rise Time1 tr2B VOL = 0.4 V, VOH = 2.0 V Fall Time1 tf2B VOH = 2.0 V, VOL = 0.4 V 1 Duty Cycle dt2B VT = 1.25 V Skew1 tsk2B VT = 1.25 V 1 tjcyc-cyc2B VT = 1.25 V Jitter, Cycle-to-cycle 1 Guaranteed by design, not 100% tested in production. MIN 2 TYP 2.3 -48 27 0.4 0.4 45 0.8 0.9 49.1 133 207 MAX UNITS V 0.4 V -27 mA mA 1.6 ns 1.6 ns 55 % 175 ps 250 ps
Electrical Characteristics - AGP, PCI
TA = 0 - 70 C; VDD = 3.3 V +/-5%, CL = 40 pF for PCI0-1, CL = 10 - 30 pF for other PCIs (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time
1 1
SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tsk1 tjcyc-cyc1 tjcyc-cyc1
CONDITIONS IOH = -1mA IOL = 1 mA VOH@MIN = 1 V VOH@MAX = 3.135V VOL@MIN = 1.95 V VOL@MAX =0.4V VOL = 0.4 V, VOH = 2.4 V VOL = 2.4 V, VOH = 0.4 V VT = 1.5 V VT = 1.5 V PCI -- VT = 1.5 V AGP -- VT = 1.5 V
MIN 2.3
TYP 0.19
MAX 0.55 -33
UNITS V V mA mA ns ns % ps ps ps
-33 30 0.5 0.5 45
68 24 1.74 1.9 50.9 150 166 168
38 2 2 55 300 250 500
Duty Cycle Skew1
Jitter, cycle-to-cycle1
1
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
12
ICS94258
Electrical Characteristics - SDRAM
TA = 0 - 70 C; VDD = 3.3 V +/-5%, CL = 20 - 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Output High Voltage VOH3 IOH = -28 mA 2.4 Output Low Voltage VOL3 IOL = 23 mA VOH = 2.0 V Output High Current IOH3 Output Low Current IOL3 VOL = 0.8V 54 1 Rise Time tr3 VOL = 0.4 V, VOH = 2.4 V 0.4 Fall Time
1 1
TYP
MAX UNITS V 0.4 V -46 mA mA 1.6 1.6 55 250 250 250 55 250 ns ns % ps ps ps % ps
0.76 0.85 49.3 243 115 213
tf3 dt3 tsk1 tsk1 tsk1
1
VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V Sdram 0:12 Sdram 0:9 Sdram 10:12
0.4 45
Duty Cycle Skew
Duty Cycle 1 Jitter, cycle-to-cycle
1
dt3 tjcyc-cyc3
45
49.3 203
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70 C; VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS IOH = -12 mA Output High Voltage VOH4B IOL =12mA Output Low Voltage VOL4B VOH = 1.7 V Output High Current IOH4B VOL= 0.7 V Output Low Current IOL4B 1 Rise Time tr4B VOL = 0.4 V, VOH = 2.0 V Fall Time
1 1
MIN 2
TYP 2.25 -48
19 0.4 0.4 45 0.96 0.95 53.8 324
MAX UNITS V 0.4 V -21 mA mA 1.6 1.6 55 500 ns ns % ps
tf4B dt4B tjcyc-cyc4B
VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V
Duty Cycle 1 Jitter, Cycle-to-cycle
1
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
13
ICS94258
Electrical Characteristics - 48MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS IOH = -16 mA Output High Voltage VOH5 IOL = 9 mA Output Low Voltage VOL5 VOH = 2.0 V Output High Current IOH5 VOL = 0.4 V Output Low Current IOL5 1 Rise Time tr5 VOL = 0.4 V, VOH = 2.4 V Fall Time
1 1
MIN 2.4
TYP 2.75 -40.5
29 1.8 45 1.8 54.5 206
MAX UNITS V 0.4 V -23 mA mA 2 2 55 500 ns ns % ps
Duty Cycle 1 Jitter, cycle-to-cycle
1
tf5 dt5 tjcyc-cyc5
VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS IOH = -16 mA Output High Voltage VOH5 IOL = 9 mA Output Low Voltage VOL5 VOH = 2.0 V Output High Current IOH5 VOL = 0.4 V Output Low Current IOL5 1 Rise Time tr5 VOL = 0.4 V, VOH = 2.4 V Fall Time
1 1 1
MIN 2.4
TYP 2.75 -40.5
29 1.1 45 1.3 54.5 428
MAX UNITS V 0.4 V -23 mA mA 2 2 55 1000 ns ns % ps
Duty Cycle
1
tf5 dt5 tjcyc-cyc5
VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V,
Jitter, cycle-to-cycle
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
14
ICS94258
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
15
ICS94258
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS94258. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS94258 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94258 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS94258. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state.
Third party brands and names are the property of their respective owners.
16
ICS94258
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLK
PCICLK VCO Crystal
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94258 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
Third party brands and names are the property of their respective owners.
17
ICS94258
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS94258. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes: 1. All timing is referenced to the internal CPU clock. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS94258. 3. All other clocks continue to run undisturbed.
Third party brands and names are the property of their respective owners.
18
ICS94258
N
c
SYMBOL
L
E1 INDEX AREA
E
12 h x 45 D
A A1
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
10-0034
D (inch) MIN .620 MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS94258yFT
Example:
ICS XXXX y F - T
Designation for tape and reel packaging Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
19
ICS94258
N
c
L
INDEX AREA
E1
E
12 D
a
A2 A1
A
In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N 0 8 0 8 aaa -0.10 -.004 VARIATIONS N 48
10-0039
-Ce
b SEATING PLANE
D mm. MIN 12.40 MAX 12.60 MIN .488
D (inch) MAX .496
aaa C
Reference Doc.: JEDEC Publication 95, MO-153
(240 mil)
6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil)
Ordering Information
ICS94258yG-XX-T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
20

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